Nanocomputing Block based Multi-Context FPGA

As the minimum dimensions of CMOS transistors shrink down to 90 nm and below, some physical obstacles have been observed which prevent rigidly this miniaturization. For example, high transistor leakage currents lead to an important increase of the 'idle' power consumption of CMOS memory arrays (e.g. SRAM). This limits a number of applications, especially for FPGA circuit as its configuration data should be hold even it is in ‘idle’ state. Many emerging nano-devices are therefore the subject of research and development to help CMOS technology continue to down-scale. Among them, the twoterminal Memory Resistor (Nanomemristor) is one of the most promising candidates thanks to its non-volatility, small dimension and reasonable compatibility with CMOS process etc. The integration of emerging nano-devices requires some novel circuits and architectures. In this paper, we present a NAnocomputing Block (NAB) based on hybrid Nanomemristor/CMOS technology to address the FPGA logic applications. Benefiting from the NAB architecture, Multicontext FPGA can be realized easily in low area. Some special techniques for hybrid Nanomemristor/CMOS design and simulations are as well as shown by using STMicroelectronics CMOS65nm design kit.